An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS

This paper presents an analog-assisted digital low dropout regulator (LDO) by adopting a delta sigma modulator (DSM) and a finite impulse response (FIR) filter for reduced output ripple. By employing a dual-mode gain-controlled voltage detector (GCVD) and a gear-shift algorithm, reduced recovery time is achieved. An exponential-ratio array (ERA) is designed to expand the load current range. A charge pump (CP) LDO as an analog-assisted loop enhances transient performance. The proposed digital LDO is implemented in 180nm CMOS. For an output voltage of 0.9V, a maximum load current of 100mA and 5500× load current range are achieved with an input voltage of 1V. The undershooting voltage is 78mV when the load current changes from 210mA to 100mA, and the output ripple is 0.37mV.