Chip Size Minimization for Wide and Ultrawide Bandgap Power Devices

Chip size ( ${A}_{\text {chip}}$ ) optimization is key to the accurate analysis of device and material costs and the design of multichip modules. It is particularly critical for wide bandgap (WBG) and ultrawide bandgap (UWBG) power devices due to high material cost. Moreover, the designs of ${A}_{\text {chip}}$ and the drift region thickness ( ${W}_{\text {dr}}$ ) and doping concentration ( ${N}_{\text {dr}}$ ) are interdependent, requiring their co-optimization. Current design practices for ${A}_{\text {chip}}$ , ${W}_{\text {dr}}$ , and ${N}_{\text {dr}}$ rely on optimizing electrical parameters. $^{^{^{}}}$ This work presents a new, holistic, electrothermal approach to optimize ${A}_{\text {chip}}$ for a given set of target specifications, including breakdown voltage (BV), conduction current ( ${I}_{{0}}$ ), and switching frequency ( ${f}$ ). The conduction and switching losses of the device are considered as well as the heat dissipation in the chip and its package. For a given BV and ${I}_{\text {o}}$ , the optimal ${A}_{\text {chip}}$ , ${W}_{\text {dr}}$ , and ${N}_{\text {dr}}$ show a strong dependence on ${f}$ and thermal management. Such dependencies are missing in prior ${A}_{\text {chip}}$ design methods. This approach is applied to compare the optimal ${A}_{\text {chip}}$ of WBG and UWBG devices up to a BV over 10 kV and ${f}$ of 1 MHz. $^{^{^{}}}$ Our approach offers more accurate cost analysis and design guidelines for power modules.