Design Wireless Communication Circuits and Systems Using Approximate Computing

In recent years, the communication circuits and systems have become more complicated and more power hungry. However, due to the channel noise and forward error correction (FEC) module, communication systems can inherently tolerate certain errors at the receiving end. Approximate computing schemes have been explored in many communication systems to achieve low complexity and low power design. This chapter introduces approximate floating point adder design with mantissa truncation and compensation method, low-complexity floating-point multiplier design with partial product location adjustment and method based on partial product probability compensation. A top-down FP FFT processor design strategy for determined accuracy requirement is proposed with several times mantissa bit-width search iteration, which achieves high efficiency. At last, two approximate polar code decoders are introduced with approximate PE units or approximate sorter design, and the hardware efficiency increased significantly with negligible BER performance deterioration.