(Invited) Selection of Channel Layer for the Vertical Oxide TFT

With the development of the virtual reality and augmented reality displays, ultra-high resolution displays become one of the big concerns. People would not be bothered by display pixels when taking closer look at display with the resolution higher than 2000 ppi. The most important factor in the ultra-high resolution display is the pixel area and the smallest TFT size would be the first criteria in the TFT point of view. Although back channel etch (BCE) TFT and self-aligned (SA) TFT have been used for driving high resolution LCD and OLED, respectively, typical planar structured TFT would not permit display with ultra-high resolution. The vertical TFT with the smallest pixel pitch value among the TFT structures is suitable candidate. Furthermore, channel length of the vertical TFT can be precisely controlled by the thin film thickness of spacer. This results in high and uniform on-current of TFT. Meanwhile, vertical TFT can also provide channel length longer than the sub-pixel length. When we have to apply high gate voltage depending on the display mode, TFT with longer channel length within smaller sub-pixel size would be necessary. One of the advantages of oxide TFTs lies in the freedom of selection of architecture, materials, and process depending on the device application. Considering the main issue in the vertical TFT, the step coverage of active layer, oxide TFT seems to be the best selection. Oxide semiconductor and gate insulator used for the oxide TFT can be deposited by means of plasma enhanced atomic layer deposition (PEALD), which provides excellent step coverage of films. One of the issues in vertical oxide TFT is the relatively high off-current depending on the mobility of TFT due to the short channel length. Here, we compare the performance of vertical oxide TFTs with the variation of semiconductor’s carrier density. By virtue of the easiness for the modifying carrier concentration of InOx based semiconductor, we could adjust the mobility of vertical TFT with low off-current. Vertical TFT with InOx shows 1.26 mA at Vg = 5 V and Vds = 2.1 V, S.S of 0.14 V/dec., on/off ratio of 10 7 , and Von of -1.8V. Meanwhile at the same driving condition, IGZO shows on-current of 0.23 mA, S.S of 0.12 V/dec., on/off ratio of 10 8 and Von of -0.2V. We will discuss the best selection for the channel layer of vertical TFT depending on the display mode and show the optimized TFT performance depending on the carrier concentration of semiconductors.