TCAD Simulation on Saddle-Fin Device Performance Boosting with Word Line Engineering

As the DRAM scales down to 1x nm, much effort has been dedicated to reduce access transistor leakage and obtain sufficient drivability to improve retention time and access speed. This paper presents the TCAD simulation studies of saddle fin device performance boosting with word line structure engineering. The dual work function WL structure which are used in the modern DRAM have been simulated and illustrated. Further, a separated dual gate and variable WL recess structure are proposed. Its improvements on the access transistor is calculated. Both have obvious suppression on the GIDL and improvement on the driving current. These results provide reference for further scaling and development of saddle fin devices