Reticle Floorplanning and Simulated Wafer Dicing for Multiple-Project Wafers by Simulated Annealing

In this chapter we have demonstrated how simulated annealing is used to solve two NPhard problems: simulated wafer dicing and reticle floorplanning problems for MPW. For simulated wafer dicing, we suggest that HVMIS-SA-Z be employed to find the wafer dicing plans, especially for low-volume production. As for reticle floorplanning, BT-VOCO and