Simulation Based Design Centering for Yield Optimization in Photonic Integrated Circuits

ABSTRACT This paper studies the use of design centering to maximize the yield of grating couplers for use in photonic integrated circuits (PICs). 2D finite difference time domain (FDTD) modelling is used to analyse the performance of the grating coupler in terms of parameters that are susceptible to process variations in deep UV lithography. The effect of fiber‐to‐chip measurement uncertainty is also included. Multi‐dimensional interpolation is used to reduce the number of required simulations and predictions of yield optimized geometrical parameters are made using typical process variations expected in PIC foundries.