Error suppressing encode logic of FCDL in 6-bit flash A/D converter

A 6 bit, 320 Ms/s BiCMOS flash A/D converter was fabricated using a new Folded Cascoded Differential Logic (FCDL). This FCDL reduces sparkle code errors caused by comparator metastability, and improves encoder operation speed. The measured error rates of a chip implemented in a 0.7 /spl mu/m BiCMOS was less than 10/sup -10/ times/sample and the chip consumes only 505 mW.