Effects of Interface Traps and Self-Heating on the Performance of GAA GaN Vertical Nanowire MOSFET

In the past couple of years, GaN-based vertical FETs have been explored to complement their potential logic applicability along with its well-known advantages in high-power and RF applications. In this article, the performances of short-channel gate-all-around (GAA) GaN vertical nanowire MOSFETs, fabricated for a possible low-voltage logic application, have been investigated via simulation, assuming the multilevel trapping effects at the gate interface and the self-heating effects. The simulation results reveal that shallow traps at the interface increase the OFF-state current, the subthreshold swing, and the drain-induced barrier lowering, while deep traps at the interface lower the ON-state current and cause the threshold voltage instability. When the gate voltage is higher than the flat-band voltage of the nanowire channel in the saturation region of operation, the mobility degradation, related to the self-heating, becomes significant due to the increased incorporation of the optical phonon scattering.