Techniques for offset calibration in comparators

This paper describes the development of the offset cancellation techniques used in comparators over the past 20 years. Comparators directly impact the Analog-to-Digital Converters (ADCs) performance, which require further advancement in their essential properties such as low offset voltage, high speed, and less resolution. With the operation of the N-stage voltage-controlled lines, the overall input referred offset voltage is reduced by a factor of √N compared to the offset voltage of a single-stage comparator. The comparator re-ordering and digital compensation are utilized to relax the offset resulted from various mismatches.