Wafer-Level Integration of Liquid Cooling Microchannel on CMOS Chips with Cu-Cu Low-Temperature Bonding Process

As big data analytics, machine learning, AI (artificial intelligence) and so on technologies impose increasingly higher performance requirements on computing chips, advanced process nodes and packaging technologies such as 2.5D and 3DIC continue to evolve. The power consumption of high-performance computing chips has surged beyond 1000W, presenting severe thermal challenges. Existing researches have shown that microchannel liquid cooling, as an active thermal management technology, exhibits superior cooling capabilities. Higher cooling efficiency can be achieved compared to traditional out-of-package solutions by embedding microchannels into packages to reduce the thermal resistance between heat sources and coolant. Consequently, in-package microchannel liquid cooling has emerged as a potential solution to address the thermal management challenges of continuously evolving high-performance computing chips. Existing researches mainly focus on the thermal performance of microchannel, paying major efforts on the design of microchannel, production in laboratories, and thermal characterization. Although various effective microchannel thermal solutions for 2.5D/3D integrated chips have been demonstrated, reports on the implementation of in-package microchannel integration processes in industrial manufacturing environments are still limited, remaining challenges on production compatibility. This work proposes a wafer-level integration of liquid cooling microchannel on CMOS chips based. The integration is validated on 8-inch platforms as a stack of microchannel wafer and CMOS wafer are yielded through 8-inch W2W (wafer-to-wafer) low-temperature Cu-Cu bonding process. The packaging employs standard FC (flip-chip) processes which are compatible with conventional packaging platforms, demonstrating substantial potential for manufacture in industrial environments. The feasibility of the proposed packaging process was shown using 8-inch TTV (thermal test vehicle) wafers. SAT (Scanning Acoustic Tomography) and so on tests were inducted to examine the process qualities at various stations such as Cu-Cu bonding, bumping, FC bonding, packaging and assembly. DSC tests and tensile tests were also performed to verify thermal and mechanical characteristics of the Cu-Cu bonding interface.