Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

As the demand for computational capabilities continues to grow, the design and optimization of arithmetic circuits have more crucial in modern digital systems. The efficient operations of these arithmetic circuits heavily depend on the performance of fundamental modules such as Full Adders (FA). In addition to addressing typical challenges, designing full adder circuits using alternative logic offers unique advantages that are vital for the developing landscape of digital system. This paper presents two FAs based an alternative structure using double pass-transistor logic (DPL). The FA cells were designed and implemented in Cadence EDA platform on gptk 45nm CMOS technology. The proposed circuits performance were compared with other conventional logic and few hybrid adders. In comparison with other logics, various type of simulation results indicate that the proposed FA-2 exhibits improved performance in terms of average power, average delay, and average power-delay product (PDP). Our proposed FA-2 shows performance improvement over conventional CMOS for Power, Delay, and PDP, with values of 3.304%, 69.017%, and 74.602%, respectively. Full adders were simulated under different supply voltages and process corners to measure the reliability and robustness. Noise tolerances of full adder circuits were calculated using Average Noise Threshold Energy (ANTE) methodology. Also, we implemented an 8-bit Ripple Carry Adder and verified the effective operation in large bit size words. Various simulations and analysis were carried out by Cadence Spectre tool .