CMOS芯片
节点(物理)
缩放比例
晶体管
电容
电子工程
计算机科学
MOSFET
逻辑门
电气工程
计算机体系结构
光电子学
工程物理
材料科学
工程类
物理
电压
结构工程
几何学
量子力学
数学
电极
标识
DOI:10.1109/vtsa.2011.5872206
摘要
This paper reviews options for CMOS scaling for the 22nm node and beyond. Advanced transistor architectures such as ultra-thin body (UTB), FinFET, gate-all-around (GAA) and vertical options are discussed. Technology challenges faced by all architectures (such as variation, resistance, and capacitance) are analyzed in relation to recent research results. The impact on the CMOS scaling roadmap of system-on-chip (SOC) technologies is reviewed.
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