Verilog-AMS: Mixed-signal simulation and cross domain connect modules

Verilog-AMS is one of the major mixed-signal hardware description languages on today's market. In addition to the extended capabilities to model analog and digital behavior, the language supports a novel approach to merge existing digital and analog designs without rewriting the individual designs. At the center of this approach is the connect module and the connection rules. These language features enable the designer to declare modules, which can be automatically or manually inserted at an intersection of net segments with different disciplines. A mapping between different disciplines and therefore between the different domains, enhances the (re)usability of designs and enables a natural approach to mixed-signal design. Circuitry of interest can be modeled with high accuracy in the analog domain whereas less critical portions of the design are modeled in the faster but less accurate digital simulation domain. Since Verilog-AMS actively supports the mixed-signal approach, the interchange of digital and analog portions is straightforward and strongly encouraged. The purpose of this paper is to introduce the semantics of Verilog-AMS connect modules in greater detail and illustrate the impacts and tradeoffs on the simulation performance. Closely related principles of driver-receiver segregation, discipline resolution and cross domain communication are discussed and evaluated to provide a thorough description of the extended Verilog-AMS mixed-signal simulation capabilities.