Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications

In this article, we have explored the impact of drain spacer length optimization in 3-Fin-Tri-gate structure and single-Fin Tri-gate structure for mid band 5G application. Tri-gate Fin-FETs at 14 nm technology node are the best candidates for 5G application. However, the driving capability of single-Fin device is very low thus it is desirable to use multi-Fin structure for relatively high frequency RF application. Although multi-Fin-FETs are prone to parasitic capacitances but show better performance in terms of transconductance $(g_{m})$ and cut-off frequency $(f_{T})$ as compared to single-Fin based Fin-FET. It has been observed that by increasing the drain spacer while keeping fin length constant, a sufficient increase in drain current in the single-Fin as well as in 3-Fin structure can be achieved. The Same variation shows a drastic improvement in 3-Fin structure in terms of parasitic capacitances, unlike the single-Fin structure. The improved drain current and reduced parasitics eventually result in a very high cut-off frequency of 479 GHz, which is 36% higher than the single-Fin structure. An extensive comparison with the state-of-the-art design shows an improvement of 25% in fT.