DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm

Recent SRAM-based in-memory computing (IMC) hardware demonstrates high energy efficiency and throughput for matrix–vector multiplication (MVM), the dominant kernel for deep neural networks (DNNs). Earlier IMC macros have employed analog-mixed-signal (AMS) arithmetic hardware. However, those so-called AIMCs suffer from process, voltage, and temperature (PVT) variations. Digital IMC (DIMC) macros, on the other hand, exhibit better robustness against PVT variations, but they tend to require more silicon area. This article proposes novel DIMC hardware featuring approximate arithmetic () to improve area efficiency without hurting compute density (CD). We also propose an approximation-aware training model and a customized number format to compensate for the accuracy degradation caused by the approximation hardware. We prototyped the test chip in 28-nm CMOS. It contains two versions: the with single-approximate hardware () and with double-approximate hardware (). The measurement results show that supports a 4 b-activation and 1 b-weight (4 b/1 b) CNN model, achieving 327 kb/mm $^2$ , 458–990 TOPS/W (normalized to 1 b/1 b), 8.27–392 TOPS/mm $^2$ (normalized to 1 b/1 b), and 90.41% accuracy for CIFAR-10. supports a 1 b/1 b CNN model, achieving 485 kb/mm $^2$ , 932–2219 TOPS/W, 14.4–607 TOPS/mm $^2$ , and 86.96% accuracy for CIFAR-10.