Novel Packaging Platform Based on Bridge Dies with Top and Bottom I/O Connections on Standard Substrates

Recently, with the advent of the artificial intelligence (AI) era, chiplet systems have emerged as a new standard platform for advanced package designs. To achieve the same high speed and bandwidth as monolithic chips, chiplets are interconnected using either an “interposer” or a “bridge.” Despite the interposer's dominant role in current packaging technology, bridge dies are gaining increasing attention due to their flexibility and cost advantages. In this study, we propose a bridge-die-based packaging platform that eliminates the need for specific substrate processing. Traditional bridge die technology requires trench formation in the substrate for die embedding due to the thick silicon portion of bridge dies. To overcome this limitation, we developed a method for removing the silicon portion while retaining the thin organic redistribution layers (RDLs). This was achieved using conventional molding and grinding processes. The proposed approach also enables electrical connections to both upper-side chips and bottom-side substrates through microbumps and flipchip bumps, respectively. Metallographic analysis revealed a wellshaped and precisely aligned morphology with uniform wetting and intermetallic formation. The final 7 × 7 package consists of two system-on-chip (SoC) dies and eight high-bandwidth memory (HBM) dies interconnected by nine bridge dies. Basic reliability tests, including preconditioning, thermal cycling (TC), and unbiased highly accelerated stress testing (uHAST), demonstrated the package's robust mechanical integrity. The proposed platform is promising as it allows the continued use of existing packaging processes and materials while offering not only low cost and high yield but also excellent mechanical stability and enhanced flexibility in package design.