High-speed DAC/ADC implementation using RFSoC FPGA for quantum computing

Quantum processing units (QPUs) require precise tuning and continuous monitoring systems to be in a functional state, including stable frequency calibration and low-latency control respecting hardware timing constraints. Such systems, however, are complex, making QPUs less appealing and out of reach for many researchers and those without specialized RF/FPGA expertise. We give a brief review of Ramsey spectroscopy, the methodology used for sensitive qubit monitoring, and use QubiC 2.0’s clock-accurate simulation architecture to bridge this gap by validating pulse programs and parameter sweeps in silico before hardware bring-up. This establishes the cornerstone for future work involving hardware-in-the-loop applications where the QPU environment is simulated to work in conjunction with a high-speed DAC/ADC RFSoC FPGA setup, enabling prototyping and real-time calibration while preserving reproducibility.