CMOS芯片
晶体管
纳米技术
半导体工业
集成电路
半导体器件制造
工程类
工程物理
计算机科学
电气工程
材料科学
制造工程
电压
薄脆饼
作者
Henry H. Radamson,Huilong Zhu,Zhenhua Wu,Xiaobin He,Hongxiao Lin,Jinbiao Liu,Jinjuan Xiang,Zhenzhen Kong,Wenjuan Xiong,Junjie Li,Hushan Cui,Jianfeng Gao,Hong Yang,Yong Du,Buqing Xu,Ben Li,Xuewei Zhao,Jiahan Yu,Dong Yan,Guilei Wang
出处
期刊:Nanomaterials
[MDPI AG]
日期:2020-08-07
卷期号:10 (8): 1555-1555
被引量:203
摘要
The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
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