A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning

The microring resonator is critical for dense wavelength division multiplexed (DWDM) chip-to-chip optical I/O, enabling modulation and channel selection at the$\upmu\text{m}$-scale suitable for a VLSI chip. Microring-based links, however, require active tuning to counteract process and thermo-optic variations. Here, we present a bit-statistical tuner that decouples tracking of optical one- and zero-levels to realize non-dc-balanced data transmission, an “eye-max”-locking controller, and self-heating cancellation without need for a high-speed sensing frontend. We implement the tuner on a 45 nm CMOS-SOI process with monolithically integrated photonic devices and circuits. The tuner consumes 0.74 mW in the logic while achieving a record 524 GHz ($>$50 K temperature) tuning range at$3.8\;\upmu\text{W/GHz}$heater efficiency. To our knowledge, this is the highest range and heater efficiency reported by an on-chip closed-loop thermal tuner to date. The tuner integrates with a 5 Gb/s 30 fJ/bit monolithic microring transmitter, achieving wavelength-lock and immunity to both tracking failures and self-heating events caused by arbitrary, non-dc-balanced bitstreams. In addition, the tuner provides critical functionality for an 11-$\lambda$DWDM transmitter macro capable of$11\ \times\ 8$Gb/s bandwidth on a fiber. Together with the transmitter, a 10 Gb/s on-chip monolithic optical receiver with$10^{-{\textbf{12}}}$BER sensitivity of$9\;\upmu\text{A}$at 10 Gb/s enables a sub-pJ/bit 5 Gb/s optical chip-to-chip link, with the bit-statistical tuner providing thermally robust microring operation.