A 40‐Msps 10‐bit video BiCMOS analog‐to‐digital converter

Abstract A 40‐Msps 10‐bit video A/D converter LSI has been developed. A 0.8‐μm BiCMOS technology is applied. The two‐step parallel type conversion scheme is adopted, using the MOS analog switch and bipolar comparator. A redundant structure is employed using 5 bits for the coarse stage and 5.5 bits for the fine stage. Three points of voltages in the coarse ladder circuit are transferred to the fine ladder resistor circuit and are used as the upper‐end, middle‐point and lower‐end voltages. Wire connection configuration for the fine ladder resistors is redesigned so that the error is reduced and the speed is improved. A high‐speed circuit with a preamplifier is used in the fine comparator. Protection functions for the overflow and underflow are also provided. With this design, the S/N ratio of 60 dB is realized, for the clock frequency of 40 MHz and the full‐scale 50‐kHz input. The designed LSI operates with the 5‐V single supply. Power consumption is 700 mW, the number of elements is 7000, and the chip size is 4.1 × 4.8 mm 2 . The following performance is obtained by overall evaluation of the printed board containing the S&H IC and DAC. The D.G. and D.P. for 40‐MHz clock are 1 percent and 1 deg, respectively. The S/N ratio is 52 dB for 10 MHz full‐scale input and 48 dB for 20‐MHz full‐scale input. A future problem involves the on‐chip implementation of the S&H circuit.