A Complete Modeling Methodology for Full-chip Parasitic Extraction

As the semiconductor process node continues to shrink, on-chip parasitics become more and more important. However, a comprehensive methodology for the extraction of parasitic parameters on a full chip has rarely been discussed in the literature. In this work, we propose a full-flow RC extraction methodology for modern circuit design, as well as a systematic benchmark framework. Considering the shielding effect, we propose a geometric distribution of the "ring" structure and three types of corresponding patterns. We adopt a spatial temporal range tree (STR tree) to obtain potential aggressors and use event-based sweeping lines to get the true aggressor for wire segmentation and environment search. To approximate the process effect on the conductor’s resistivity, we assume a fixed metal density to obtain the corresponding resistance per square (RPSQ) and then experiment to obtain the optimal metal density. The experimental results show the effectiveness of our methodology and demonstrate that our extractor performs better than OpenRCX and PEX on multiple metrics.