P‐1.37: The Impact of Polysilicon Low Power Etching Process on LTPS TFT Characteristics and Reliability

This paper investigates the effects of different polysilicon etching powers on the electric characteristics of low temperature polycrystalline silicon (LTPS) thin‐film transistors (TFTs). The study reveals that lower etching powers result in a weaker hump effect in the TFT Id‐Vg curves. The influence is more pronounced in TFTs with narrower channel widths. Despite minimal differences in the taper of polysilicon film after dry etching with different powers, the stability of TFTs under positive bias temperature stress (PBTS) degrades with increasing dry etching power, indicating that plasma intensity may induce damage to the edge of the polysilicon channel. When the etching power is reduced from 18 kW to 9 kW, the Vth shift is reduced by 25% after 10000 s PBTS at 70 °C. This results could lay the foundation for achieving high‐reliability flexible backplane for AMOLEDs.