Functional mapping for nanodevice-based architectures

Recently, technology advancement led to the emergence of nanodevice-based architectures. By exploiting the fine-grain dynamic reconfigurability of these logic cells, nanodevice-based architectures are expected, compared to conventional architectures, to reduce area and cost, and improve performance over a broad range of applications. In order to explore the potential of these architectures, the definition of new CAD tools is required. This paper discusses the challenges for system-level exploration for nanodevice-based architectures and proposes an approach enabling automatic application partitioning and mapping for these architectures.