NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures

N- and P-MOSFETs have been fabricated in various epitaxial layer structures containing relaxed Si/sub 1-x/Ge/sub x/, and strained Si active regions. Theoretical calculations predict that the strain-splitting of the conduction bands should produce a higher bulk electron mobility in strained Si. Enhanced electron mobilities have recently been observed in n-type modulation-doped structures employing strained Si. In this work we demonstrate NMOS transistors with peak room temperature electron mobilities which are a factor of 2.2 larger than those measured in devices fabricated in CZ Si substrates. By comparing the behavior of buried- and surface-channel structures, we have observed mobility enhancements associated with both the separation of the electrons from the semiconductor/oxide interface, and the strain-induced band splitting. The room temperature performance of PMOS devices fabricated in such structures is not significantly different from that of the Si control devices.< >