The defect mitigation on EUV stack by track based technology

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the second generation of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. A typical defect Pareto for EUV line-space patterning is dominated by bridging defects and pattern collapse. Regarding pattern collapse, careful attention needs to be paid to optimizing the rinse process to avoid the large forces that cause collapse during drying. In this paper, we present an optimized rinse technology that works to prevent that pattern collapse, especially on EUV line/space patterns below 40nm pitch. Additionally, this paper reviews the ongoing progress in track-based processes (coating, developer) that are required to enable EUV patterning. This work is especially focused on defect mitigation during film coating and resist developing processes, which have a direct effect on the occurrence of bridging defects during pattern transfer.