中间层
材料科学
过程(计算)
有限元法
模具(集成电路)
电子工程
制作
钥匙(锁)
集成电路封装
计算机科学
序列(生物学)
理论(学习稳定性)
图层(电子)
机械工程
信号处理
制造工艺
工艺工程
引线键合
过程集成
信号(编程语言)
工程类
作者
Ching-Feng Yu,Chao-Kai Hsu,Chih-Cheng Hsiao
标识
DOI:10.1109/impact67645.2025.11281668
摘要
This study proposes an enhanced chip-first process flow, inspired by the Hyper-RDL (HRDL) architecture, for fabricating 3D heterogeneous wafer-level packages with exceptionally low warpage. By reordering key manufacturing steps—performing die mounting, overmolding, and back-thinning on fully supported carriers prior to the final low-temperature (below 250 °C) Cu-PI hybrid bonding of the upper and lower modules—this novel sequence effectively preserves the dimensional stability of all components. This approach successfully limits the final package warpage to less than 100 μm on a 300 mm glass carrier while achieving high-resolution features, including 2 μm line/space (L/S) and 6 μm through-mold vias. Finite element analysis, validated with experimental data at multiple process stages, confirms the model's high accuracy, with prediction errors as low as 0.6% for complex overmolding steps. The proposed process offers a robust pathway for manufacturing ultra-flat, high-layer-count organic RDL interposers that outperform both conventional semi-additive processing (SAP) and baseline HRDL technologies in terms of warpage control.
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