A 0.0035-mm2 0.42-pJ/bit 8–32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE

This paper presents an ultra-compact reference-less continuous-rate clock and data recovery (CDR) circuit. An adaptively-biased charge sharing (AB-CS) integrator is devised to significantly shrink the CDR's core area, thus, reducing the length and loading capacitance of the clock distribution for power saving. Meanwhile, the charge/discharge step of our ABCS integrator is reduced by our developed adaptive bias circuit to lower the integrated jitter of the recovered clock. Our Alexander phase-frequency detector (A-PFD) is introduced to enable continuous-rate reference-less operation with a small area and low power. A 1-tap decision feedback equalizer (DFE) is embedded by the DFE-merged slicer with low power and negligible extra area. Fabricated in a 40-nm CMOS, our CDR prototype merely occupies 0.0035-mm2 core area and achieves an 8-to-32-Gb/s capture range, 0.42-pJ/bit energy efficiency, 421.4-fs clock jitter, and <1$0^{-12}$ bit error rate with a PRBS-31 input stream.