Warpage Engineering in C2W Hybrid Bonding Using Inter-Die Gap Fill Dielectrics for 2.5D/3D Integration

The rapid advancement of artificial intelligence applications is continuously increasing the demand for highperformance computing. Conventional interconnect technology based on micro bump has pitch scaling, reliability, and bandwidth density limitations. In recent years, hybrid bonding has emerged as an essential packaging technology that achieves higher bandwidth and interconnect density. Dielectric film quality is important in achieving sufficient interfacial bonding energy for hybrid bonding. Wafer-level and chip-level bows are critical for 2.5D/3D die stacking. The CTE mismatch of Cu, Si, and oxide films leads to severe die-level warpage, impacts die tacking, and results in die drop or extensive void formation. This study focuses on characterizing dielectric materials (film thicknesses and stress profiles) coupled with different volume fractions of Cu in RDL to optimize wafer-level bow and enable chip-to-wafer (C2W) hybrid bonding. The work is further extended to optimize the inter-die gap fill (IDGF) oxide stress profile to limit substrate wafer bow to meet the tool specifications. The optimized film profiles are expected to enable multi-chip 3D stacking on reconstituted C2W hybrid bonded substrate wafer.