Wafer shape control in semiconductor manufacturing

Dielectric films have traditionally been used to address warp (referred to as Out of Plane Distortion (OPD) henceforth) caused during wafer processing. However, such films usually exhibit uniform stress and can only address global parabolic warp when the film thickness is held constant. This approach fails when wafers exhibit a so-called “saddle shape” caused by directional patterning involving word lines and bit lines. It also does not address local warp in the wafer caused by patterning density variations due to the layout of the device. This local warp can pose challenges to “chuckability” of the wafer and can lead to issues with film thickness uniformity, CD uniformity, besides influencing the In Plane Distortion (IPD) of the wafer resulting in overlay/edge placement issues during patterning steps. This paper proposes an innovative approach that combines film deposition with a subsequent ion implantation step to modulate the stress on the wafer. In this approach, the dielectric film(s) stack serves as a Stress Compensation Layer (SCL), while the subsequent ion implantation selectively modifies the stress on the SCL. This approach is shown to address both the anisotropic global wafer warp as in the aforesaid saddle shape and local warp, simultaneously resolving issues with chuckability and device overlay. Co-optimization of the film properties such as stress and thickness along with implant parameters such as species, energy and dose allow maximum entitlement for warpage correction. The paper discusses key challenges and implementation of this optimization technique in High Volume Manufacturing (HVM) for memory devices with a special emphasis on 3DNAND and High Bandwidth Memory (HBM) device integration.