电感器
放大器
极高频率
晶体管
材料科学
拓扑(电路)
光电子学
电气工程
CMOS芯片
物理
电子工程
计算机科学
工程类
电信
电压
作者
Kyung-Hwan Kim,In-Ho Choi,Kangseop Lee,Seung-Uk Choi,Jiseul Kim,Chan-Gyu Choi,Ho-Jin Song
标识
DOI:10.1109/tmtt.2022.3232167
摘要
Stacked-FET topology is analyzed to increase the output power of a power amplifier (PA) in the millimeter-wave (mm-wave) band. In the mm-wave band, parasitic capacitances of the transistor severely degrade stacking efficiency due to the phase mismatch between stacked FETs. The phase-compensation (PC) inductances, including the losses of the inductor for the best stacking efficiency, are presented in both series and shunt connections. From this analysis, a triple-stacked-FET PA is designed in the F -band. Proper PC series or shunt inductor types are used between the first and second stacked FETs and between the second and third stacked FETs in consideration of the core layout and inductor size. The PA is fabricated in the 28-nm CMOS fully depleted silicon-on-insulator (FD-SOI) process. With a compact core area of 0.054 mm 2 , the PA achieves peak PSAT and PAE MAX of 15.1 dBm and 18.6%, respectively.
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