Source/drain epitaxial thickness scaling effects on DC performance and RC delay in stacked nanosheet gate-all-around FETs

Abstract This work investigates the impact of scaling source/drain ( S / D ) epitaxial thickness on the DC characteristics and circuit-relevant RC delay of stacked nanosheet gate-all-around field-effect transistors. Three-dimensional S / D geometries are constructed using a lattice kinetic Monte Carlo-based selective epitaxial growth model, and the epitaxial thickness is systematically varied while keeping doping concentration, thermal budget, and contact resistivity fixed to isolate purely geometric effects. Reducing the epitaxial thickness enlarges the effective contact area and shortens the current transport path, thereby lowering the external resistance and enhancing the on-state current. Simultaneously, the smaller dopant reservoir suppresses dopant diffusion toward the channel, reducing the off-state leakage without introducing a conventional on-/off-current trade-off. The total gate capacitance, extracted under quasi-static off-state conditions, exhibits an opposite trend between the two contact schemes: it decreases in the top-contact (TC) configuration owing to reduced gate-to- S / D overlap, whereas it increases in the wrap-around contact (WAC) configuration due to enhanced gate-to-metal fringe coupling. Despite these competing capacitance responses, the overall RC delay improves monotonically for both configurations, as the reduction in external resistance dominates. The improvement is more pronounced in TC devices, while WAC devices show a partially saturated gain attributable to their larger baseline contact area and persistent capacitance coupling.