A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp

Pipelined ADCs are widely used for high-speed high-resolution applications, but there are two challenges. First, limited by the kT/C noise requirement, its 1 ^st -stage sampling capacitor has to be sufficiently large (e.g., several pF). This poses significant burdens for the ADC driver and the reference buffer, leading to high design complexity and huge power/area costs on the system level, especially when high linearity, high sampling rate, and low supply voltage are required. Second, it is challenging to design a low-power, high-speed, and PVT-robust residue amplifier in an advanced process. To address these two challenges, this work proposes a PVT-robust ring-amp with kT/C noise cancellation capability. It enables a 1.3mW 200MS/s 67dB-SNDR pipelined ADC with only 128fF input capacitance.