Ab Initio Investigation of Charge Trapping Across the Crystalline-Si–Amorphous-SiO2 Interface

The charge trapping that occurs at a semiconductor/dielectric junction is an important issue in semiconductor physics, $e.g.$ for MOSFETs. Unfortunately, first-principles research here is complicated by many technical difficulties. This study provides a general, integrated framework, including structure construction, GPU-accelerated DFT calculations, and Marcus theory, to study the charge trapping from crystalline Si to defects in amorphous SiO${}_{2}$. The results shed light on critical questions concerning what dominates the trapping rate, how hopping decays with distance, and how large fluctuations are induced by the amorphous nature of the dielectric.