A Resistive Random Access Memory Addon for the NCSU FreePDK 45 nm

During the past few years, resistive random access memory (RRAM) have been widely studied for a large set of applications (neuromorphic computing, nonvolatile digital design, in-memory computation, etc.) due to its promising characteristics such as high-speed operations, nonvolatile retention, and low-power consumption. As a result, many SPICE RRAM models have been proposed to allow proper circuit-level simulations. However, physical design is a problem when it comes to full-custom RRAM-based layout and electronic design automation verification since no RRAM-based process design kits are publicly available. Consequently, evaluating the benefits and the metrics of RRAM-based systems at the circuit and chip levels in term of area is an issue. Indeed, many RRAM-based systems area results are based solely on the RRAM and transistor device count and not on the exact layout area, potentially leading to inaccurate results. In this paper, we propose an addon describing a CMOS compatible RRAM technology, for the NCSU FreePDK 45 nm. The addon comprises of the Stanford RRAM Verilog-A model, fitted on published experimental results as well as a set of design rule check and layout versus schematic rules for Calibre to ensure the correctness of the physical designs. We demonstrate the benefits of the proposed addon through three case studies to show that accurate RRAM-based systems area evaluations can be obtained at both circuit and chip levels.