A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit

In this brief, a low quiescent output-capacitor-less NMOS low-dropout regulator using a coarse-fine charge-pump circuit is proposed. The proposed charge-pump low-dropout regulator (CP-LDO) achieves the output-capacitor-less LDO using a NMOS power transistor, a comparator, and a coarse-fine charge-pump circuit. It reduces both the quiescent current and the capacitor size of the charge-pump by directly adjusting the gate voltage of the NMOS power transistor. It improves both the transient response and the quiescent power efficiency by coarsely and finely adjusting the gate voltage, respectively. This also can remove the output glitch voltage. The proposed CP-LDO was fabricated using a 65nm CMOS process. Its area is 0.01 mm ² . The maximum undershoot voltage is 108 mV when the load current changes from 0.5 mA to 10.5mA within the edge time of 1ns. The total capacitor of the CP-LDO is 7.6 pF. The quiescent current is 162 nA at VIN = 0.5 V and f _CLK = 1 MHz. The figure of merit is 0.0013 ps.