Optimization of 1700V 4H-SiC JBS Diode Parameters

The in-depth design optimization of the active layer of the 1700V class 4H-SiC JBS/MPS diode structure is discussed. The important design parameters such as junction depth ( d ), width ( w ) of p + areas, and spacing ( s ) between them were optimized for the best possible trade-off between the unipolar ON-state voltage drop, the OFF-state breakdown voltage, and the bipolar surge current capability. The optimization was performed using a state-of-the-art simulator using device models calibrated on a commercially available JBS rectifier. The results show that the spacing s between the p + regions is the most decisive parameter which has to be properly designed according to the required voltage class. For the 1700 V voltage class, s should be between 2 to 4 μm and the s / w ratio should be kept low. The depth d of the p + pattern has a pronounced impact on the ignition of bipolar action such that with decreasing d the surge current capability decreases significantly.