Design of low‐voltage low‐noise operational transconductance amplifiers for low frequency applications

Abstract Low‐noise and low‐voltage operation is prime requirement of an operational transconductance amplifier for low frequency applications. However, achieving low‐noise operation at low supply voltages is a challenging task in CMOS technology owing to noise‐power and noise‐stability tradeoffs. This article outlines, the design of four differential bias self‐cascode (DBSC) operational transconductance amplifiers (OTAs) working at ±0.7 V. The four design techniques namely gate driven (GD), bulk driven (BD), bulk driven quasi‐floating gate (BDQFG), and gate driven quasi floating bulk (GDQFB) have been applied on DBSC OTAs. The designing aspects and performance parameters of these four OTAs such as gain, gain‐bandwidth, input referred noise ( IRN ), settling time (ST), common mode rejection ratio (CMRR), total harmonic distortion, input impedance, transconductance, power consumption, area consumption and process/mismatch variations have been fairly compared in this work. These DBSC OTAs have been designed and simulated using a standard 0.18‐μm 6M1P CMOS N‐well process. The results infer GD DBSC OTA shows high CMRR of 125.83 dB. While the BD DBSC OTA consumes very low power of 0.2 μW. The BDQFG DBSC OTA shows low 1% ST of 24.83 μS. The GDQFB DBSC OTA show high transconductance (2.35 mS), high gain (64.97 dB), and low IRN (0.40 μV/√Hz at 10 Hz). The theoretical predictions for these OTAs agree with the post‐layout simulations. The proposed OTAs can be used for designing various analog circuits such as programmable gain amplifiers, variable gain amplifiers, and transimpedance amplifiers for low‐frequency biomedical and health care applications.