电阻器
晶体管
泄漏(经济)
电子工程
工艺角
灵敏度(控制系统)
稳健性(进化)
等效电路
电子线路
香料
逻辑门
电路可靠性
拓扑(电路)
蒙特卡罗方法
集成电路
计算机科学
电路设计
可靠性(半导体)
指数函数
过程(计算)
离散电路
非正面反馈
工程类
网络拓扑
正面反馈
电气工程
空隙(复合材料)
半导体器件制造
集成电路设计
网络分析
电容器
半导体器件建模
电路提取
短路
材料科学
MOSFET
作者
Changle Zhi,Lihang Wang,Gang Dong,Sirui Yin,Jiaji Ma,Xiaoxian Liu,Zhangming Zhu
标识
DOI:10.1109/tim.2025.3626983
摘要
In post-bond through-silicon vias (TSVs), existing detection techniques suffer from insufficient defect type coverage, limited detection accuracy, and high sensitivity to process-voltage-temperature (PVT) variations. To address these limitations, this paper proposes a post-bond TSV detection circuit based on a cross-coupled transistor pair with a positive feedback mechanism. The proposed circuit sequentially detects bridge, open, void, and leakage defects by reconfiguring a transmission-gate switch array and a resistor network, utilizing the exponential gain of positive feedback to enable precise discrimination of minute resistance variations. The symmetric topology ensures stability, even under device mismatches and PVT fluctuations. Worst-case PVT corner simulations and Monte Carlo simulations demonstrate that the circuit can reliably detect void defects down to 10 Ω and leakage defects of 4 KΩ within microsecond-scale test durations, with statistical analysis confirming robust performance against process variations. Compared to conventional methods, the proposed design achieves better defect-type coverage, finer discrimination of defect degree, and enhanced immunity to process variations. These results demonstrate the potential of the proposed circuit to improve yield and reliability in 3-D integrated circuits employing TSVs.
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