Roles of Trap States in the Dynamic Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Bias Stress

This article investigates the effects of different kinds of trap states on the degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under alternating current (ac) gate pulse bias stress. P-type TFTs with different ON-state and subthreshold characteristics are fabricated, and thus, different distributions of donor-like tail states and deep states are achieved. The decrease of ON-state current is the dominant degradation phenomena for all the TFTs due to trap state generation occurring during the pulse rising edges. TFTs with higher donor-like trap states show severe degradation. It is attributed to the higher transient lateral electric field and hole concentration due to the higher donor-like deep state density, while acceptor-like trap states do not contribute to the degradation of p-type poly-Si TFTs under ac gate bias stress.