Mobility enhancement over universal mobility in (100) silicon nanowire gate-all-around MOSFETs with width and height of less than 10nm range

Systematic study has been performed on carrier mobility in sub-10nm gate-all-around (GAA) Si nanowire (NW) FETs on (100) SOI. The NW height is 4 - 10nm and the minimum NW width is shrunk to 5nm. For the first time, higher hole mobility than universal mobility is experimentally observed in 9nm-wide NW and even in 5nm-wide NW, demonstrating great advantage of NW pFETs, while electron mobility degradation is minimized in NW nFET. In addition, it is found that further mobility enhancements can be obtained in Si NWs by strain engineering. Underlying physical mechanisms are discussed.