FN-tunneling-current Modeling in a Recessed-channel Structure

The FN-tunneling gate-current model for the three-dimensional recessed-channel structure including a geometrical effect is obtained. Further, the measurement results in the fabricated 60-nm DRAM chip are well fitted using our modeled simulation results in consideration of the cylindrical coordinate and the poly-depletion effect. As the recessed structure was scaled down to sub-50-nm technology with a very thin oxide thickness and a small radius, for which the reliability issues were considered, the geometrical effect seriously affected the memory-sensing margin. Our model presents a sound solution for the attainment of a fast and accurate FN-tunneling gate current to resolve the reliability issues of memory-cell transistors.