C2RTL: A High-level Synthesis System for IP Lookup and Packet Classification

IP lookup and packet classification are two core functions of a router. IP lookup involves performing the longest prefix match (LPM) of the destination IP address. Packet classification involves finding the best match in a multi-field ruleset where each field needs an exact or prefix match. ASIC based IP lookup and packet classification are traditionally designed in a register transfer level (RTL) hardware description language (HDL) such as Verilog or VHDL. However, manually writing hardware logic is notoriously complicated and painful. This paper presents a High Level Synthesis (HLS) system named C2RTL. C2RTL generates hardware logic in Verilog RTL directly from IP lookup or packet classification algorithm implemented in C. C2RTL is implemented as a plugin of GCC compiler. It takes an IP lookup or packet classification algorithm (in C) as an input and generates corresponding synthesizable Verilog RTL code for pipelined ASIC. We developed several IP lookup and packet classification algorithms in C2RTL and generated corresponding Verilog RTL. We evaluated the resulting RTL code with OpenROAD EDA.