Packaging of (650 V, 150 A) GaN HEMT with Low Parasitics and High Thermal Performance

Gallium nitride (GaN) power HEMTs are challenging to package due to their high heat-flux density and requirement for low package parasitic inductances necessary to support high-switching frequencies. In this work, we developed a packaging approach based on embedding the GaN bare dice between a printed-circuit board (PCB) interposer structure for terminal interconnection and a direct-bond-copper (DBC) substrate for heat extraction. The approach was demonstrated by fabricating single-chip packages and two-chip half-bridge modules of a (650 V, 150 A) GaN HEMT. Pressure-less silver sintering was used to interconnect all of the device terminals. Simulations of the packages yielded a power-loop parasitic inductance less than 0.5 nH and a junction-to-case thermal resistance less than 0.2 °C/W. The fabricated packages were tested for static and switching performance.