Analysis and design of a high-speed low-power hysteresis CMOS comparator

A high-speed low-power CMOS comparator with internal hysteresis effect is proposed.The comparator consists of a preamplifier followed by a positive feedback stage and an output stage.With hysteresis effect,this comparator restrains the noise signal effectively.An experimental chip is fabricated using 0.35μm CMOS process.Experimental results show that the proposed comparator exhibits 100MHz operational speed with 3.3V supply power and 0.2mW power consumption at comparison rates as high as 20MHz.This comparator can be used to A/D converters.