In‐Chip Mechanical Reliability Characterization and Modeling of CMOS‐Based Memristor for 3D Integration

Abstract 3D integration with thinned memristor dies or wafers enables energy‐efficient and lower‐latency computing in data‐intensive applications. However, mechanical stresses induced by warping, bonding, and interconnects during stacking package can critically impact device reliability. Despite this, in‐chip mechanical reliability characterization and modeling for memristor‐based chip for 3D integration remain unexplored, limiting their practical deployment. Here, a comprehensive study is performed on the in‐chip mechanical reliability of memristors based on a thinned complementary metal‐oxide‐semiconductor (CMOS)‐integrated memristor chip. Chip‐level statistical analysis demonstrates that outward mechanical stress can regulate ion/oxygen vacancy migration in conductive filaments, thus affecting forming voltage, SET/RESET voltages, and retention properties. A comprehensive mechanical stress‐related model is further developed to quantify reliability degradation of the memristor chip and evaluate its impact on in‐memory computing. These findings provide a new insight into the mechanical reliability of CMOS‐integrated memristor chip for 3D integration.