Trade-off between gate leakage current and threshold voltage stability in power HEMTs during ON-state and OFF-state stress

We present a detailed investigation of the impact of electron gate leakage on the threshold voltage stability of normally-off GaN HEMTs with p-GaN gate. The analysis is based on combined DC, pulsed and transient measurements, carried out on two test wafers with different gate processes, resulting in different levels of gate leakage current. The key results demonstrate: (a) the existence of four different charge-trapping processes, whose interplay determines the sign and amplitude of the threshold voltage variation; (b) a reasonable increase in gate leakage is beneficial for eliminating the negative threshold voltage instability under positive gate bias, and for substantially reducing the positive threshold shift under off-state stress. Furthermore, (c) we present a proper characterization methodology for device understanding.