| 标题 |
First EUV-Enabled Integration Route for 50 nm Pitch N and PMOS Transistors with 2D Materials Channel from a 300 mm Fab |
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| 其它 |
期刊:2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 作者:T. Schram; Q. Smets; G. Arutchelvan; C.-H. Yao; S. Chou; et al 出版日期:2026-06-14 |
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(2025-6-4)