Asynchronous Logic as Counter Measure against Power Analysis Attacks

Cryptographic devices are vulnerable to so-called Side Channel Attacks. As attackers become smarter, hardware designers and chip manufacturers need to keep up with the security demands against these Side Channel Attacks. Side Channel Attacks such as timing analysis, power consumption analysis or electromagnetic analysis, are based upon the principle that the attacker observes the behavior of the side channel (power, electromagnetic emission etc.) while a cryptographic device is performing its operations. The side channel reveals the attacker valuable information about the secret key which ultimately enables the attacker to derive the secret key. There are several counter measures that minimize the side channel information. This thesis analyzes the influence of using asynchronous logic as a practical countermeasure against Power Analysis attacks by implementing the AES Rijndael cryptographic algorithm in a FPGA device. A Power Analysis attack is a form of a Side Channel Attack where the attacker observes the behavior of the the power consumption during a cryptographic operation. A feasible asynchronous logic design style is chosen and implemented in a FPGA. In order to compare its effectiveness, a synchronous (clocked) hardware design is made in the same design structure of the AES algorithm. Power Analysis attacks are performed on both designs, and the results are compared.