Parasitic Mismatch Mitigation for Fast Switching Modular Power Semiconductor Devices

This paper centers around analyzing the impacts of device and circuit mismatches on paralleling the silicon carbide (SiC) MOSFETs in a high-frequency power converter. A multi-variable time dependent analytical model for the gate to source voltages ( $V_{GS}$ ) of paralleled devices is developed for a comprehensive theoretical analysis. Consequently, this paper reveals the design method for the gate resistors for mitigating the influences of device and circuit parasitic components that are inherently present in a group of paralleled MOSFETs. Furthermore, a real-time dead-time tracking, based on the parameters extracted from the derived gate-charge analytical model to prevent false triggering due to the coupling effect between two devices having ultra-high voltage slew rate (dv/dt) in the mismatched half-bridge module, is carried out in the digital signal processor (DSP) environment. Case-by-case study incorporating a single parasitic component at a time is simulated and presented to validate the design process derived from the multi-variable analytical model. Experimental results captured from a modular Non-Inverting Buck-Boost (NIBB) prototype validate the theoretical analysis corresponding to the gate driver design process of paralleled devices and the dead-time optimization to suppress false triggering in the mismatched half-bridge. Finally, the proposed mechanism is employed to guide the gate driver peripheral circuitry design for a 200W all-SiC based modular PWM converter proof-of-concept.